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Category: Lecture+Lesson, 4 SWS
ECTS: 6, Sommer Semester
University of Bremen
Lecturer: PD Dr. Stefan Bosse
This lecture is intended to illustrate the increasing importance of parallel data processing in computer science and hardware chip design. Parallel processing concepts are well known in algorithms and software engineering for several decades. An algorithm is partitioned into subprocesses that are run in parallel and concurrently on several processors. However, applications of parallel and distributed algorithms have so far often been in the area of computer-intensive numerics. The development tends to create more powerful microprocessors, with the result of increasing complexity and much more important with an increase in electrical power consumption. It can be shown that the decomposition of a complex system into a system of cooperating less complex systems with the same overall computing performance has significant advantages:
The structures and algorithms known from classical multiprocessing techniques can be transfered under certain constraints in the design of digital logic systems so that a hardware design can be made with software engineering models, e.g. Multi-process models with interprocess communication primitives such as semaphores or queues. The trend in the hardware design therefore goes towards the sea-of-processor concepts with up to 1000 (simple) processor cores on a single chip. In this hardware design, system partitioning and communication play a central role. A combined hardware software co-design is essential here.
The course content is structured as follows: Classical multiprocess model with communicating sequential processes including process algebra, discussion of synchronization, extension of the classical CSP model with competition and global shared resources, mapping this extended CCSP model on Register-Transer architecture level, and finally discussing the properties of parallels and distributed systems in general. The examination consists of an oral final examination.